In an effort to realize a high-speed and highly integrated nonvolatile memory, development of phase change memories is now under way. The phase change memory is described in Non-patent documents 1, 2, and 3 and JP-A No. 100084/2003. As described in 2002 IEEE International Solid-State Circuit Conference, Digest of Technical Papers, pp. 202-203, the phase change memory employs a phase change material called chalcogenide as a resistive memory element, and stores information by taking advantage of a property of this material that the resistance of the storage element changes depending on the state of the phase change material. A write to the phase change resistor is performed by supplying a current to heat it, and thereby changing the state of the material. Raising the resistance (amorphousize), also called a RESET operation, is done by maintaining it at a relatively high temperature, whereas lowering the resistance (crystallize), also called a SET operation, is done by keeping it at a relatively low temperature for a sufficient period of time. A read from the phase change material is performed by supplying a current that is not so large as to change the state of the phase change resistor.
2002 IEEE International Electron Devices Meeting, Technical Digest, pp. 923-926 and JP-A No. 100084/2003 describe the properties of the phase change resistor, and 2003 Non-Volatile Semiconductor Memory Workshop, Digest of Technical Papers, pp. 91-92 discusses a memory cell composed of phase change resistors and NMOS transistors.
These documents discuss the potentialities of the phase change memory not only as high-speed ROM (Read-Only Memory) but also as non-volatile RAM (Random Access Memory), and also refer to the realization of the unified memory having both ROM and RAM functions. For the phase change memory, the smaller the electrode surface area of the phase change resistor, the smaller power required to change the phase change resistance, thus facilitating the scaling. In addition, since the phase change resistance changes greatly, high-speed read operations can be achieved. For these reasons, it is expected that high-speed nonvolatile memory using the phase change memory will be realized.
Furthermore, in order to realize the high-speed nonvolatile memory as described above, ferroelectric memory using a ferroelectric material as storage element is proposed. The ferroelectric memory employs a ferroelectric material as the insulator of a capacitor of the storage element, and stores information depending on its polarization. A write to the ferroelectric memory is performed by applying a voltage to the storage element to change its polarization. JP-A No. 124377/1996 points out a problem that if a potential difference occurs across the capacitor of the storage element during power off, the polarization of the ferroelectric is reversed, resulting in a destruction of the stored data. As a solution to this problem, this Patent document discloses an internal circuit that sets all the word lines at unselected level. Also, JP-A No. 124379/1996 shows a problem that a potential difference occurs across the capacitor of the storage element during power on and thereby the polarization of the ferroelectric is reversed, destroying the stored data. As a solution to this problem, a technology that causes the bit and plate lines to be at the same potential is disclosed in this document.